MODERN DIGITAL MODULATION TECHNIQUES

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This invention relates to error correction of a received data stream and more particularly to an error correction method and system which employs ambiguity zone detection, permutation and inverse permutation and iterative processing to perform the error correction action. A primary objective of any digital communication system is to transmit information at the maximum possible rate and receive it with minimum errors or distortion.

Similarly, a main design objective of data storage system is to allow the system to store information with the maximum possible density and to retrieve it with the least possible errors. A variety of error control coding schemes, channels with constraint, and digital modulation with constraint have duobinary signaling and decoding activities devised to improve data transmission and recording systems.

Error control codes such as block codes and convolutional codes are usually applied to digital sequences for the purpose of coping with errors duobinary signaling and decoding activities may happen in bursts as well as randomly.

The encoded sequence then contains some constraint or redundancy. Such constraint is then exploited by the receiver to identify possible errors that may exist in the received sequence. For example, if the received sequence does not satisfy parity-check equations, then the receiver detects the existence of some errors and, in some cases, can correct them.

In order to achieve a higher performance, a concatenation of two error correcting codes is sometimes adopted. Here the term "inner encoder" is used in the sense that the inner encoder is closer to the communication channel. Hence a subsystem including an inner encoder, the communication channel and an inner decoder, is often called an "outer channel".

The outer encoder therefore sees the outer channel as the effective channel. An example is to use a block code e. An "interleaver" is often placed between the two encoders, because when the inner decoder makes erroneous decisions, it tends to create bursts of errors due to the nature of the convolutional code. An interleaver is an example of a device which permutes a data stream in a manner which is reversible. An example of an interleaver is shown in FIG. An output is obtained by sequentially accessing adjacent columns of bits.

The interleaving action disperses adjacent bit values and prevents a burst error from affecting a sequential run of bits in the original data stream. By having the interleaver in front of the outer channel, the outer encoder and decoder do not have to deal with long bursts of errors.

Fundamentals and Applications, Prentice-Hall, The type of system represented in FIG. The notion of concatenated system can be generalized to a system in which the inner encoder is not a conventional error correcting encoder such as a block code or convolutional codebut is a special type of signaling scheme or a channel with some constraint or memory. A number of coding techniques have been developed to reduce adverse effects due to duobinary signaling and decoding activities factors.

Partial-response channel coding is well recognized as a bandwidth-efficient transmission technique and can be duobinary signaling and decoding activities as a technique to shape the signal spectrum by introducing a controlled amount of ISI. An optimal decoding structure for a partial-response channel is known as maximum-likelihood ML decoding See e.

A system with partial-response channel coding and maximum likelihood duobinary signaling and decoding activities has become popular in recent years and is often referred to as a PRML system see e. Another class of codes, often used in digital recording, is run-length limited codes, denoted d,k -limited codes.

The integer parameters d and k represent the minimum and maximum numbers of runs of either 0's or 1's that are allowed in the encoded sequence. The lower bound duobinary signaling and decoding activities is chosen from the Duobinary signaling and decoding activities consideration, and the upper bound k is set to insure clock synchronization capability at the receiver side. Both partial-response channels and run-length limited codes can be viewed as techniques that introduce some constraints into the digital sequence to be transmitted.

Such constraints or memory should be exploited by the receiver to identify possible errors or biases that may exist in the received sequence. Techniques similar to partial-response signaling have been developed in digital modulation schemes. One important class of such modulation techniques is known as continuous phase modulation CPM or continuous envelope coded modulation see e.

Here, some constraint is introduced in the modulated signal, because the phase values that the modulated signal is allowed to take are limited to a subset of the set of phase values defined for the modulation system. An example duobinary signaling and decoding activities CPM is MSK minimum shift keying in which the phases that the modulated signal is permitted to take at a given symbol time are only the phases adjacent to the previous symbol phase.

Another class of digital duobinary signaling and decoding activities modulation techniques duobinary signaling and decoding activities similar properties is those that use differential precoding of the data.

In this case, the correlation is caused by the preceding and consequent duobinary signaling and decoding activities. Since the amplitude of transmitted signals contains no information, one can reproduce the original information even if the amplitude has been significantly distorted. These classes of digital modulation techniques have come to be predominantly used in wireless communication systems.

Instead of concatenating two error control codes, an error control code may be concatenated with digital modulation. A trellis-coded modulation TCM is a well-known example in which a convolutional code and digital-phase modulation are combined. The receiver can correct most errors effectively, since the duobinary signaling and decoding activities can exploit the constraint that the received phase sequence must satisfy.

An optimal decoding structure for continuous phase modulation, precoded digital phase modulation and TCM is maximum-likelihood ML decoding, similar to that originally derived for convolutional codes i. A receiver may be designed to decide that a symbol should be erased when it is received ambiguously.

Suppose that a channel input is binary, i. When a received symbol is corrupted by strong noise or interference and its value is near the threshold between 0 and 1, then the duobinary signaling and decoding activities may opt not to make a hard decision regarding the value of the symbol, and labels it as "e", which stands for an erasure.

To implement an erasure, a quantizer is required with duobinary signaling and decoding activities threshold ssee FIG. When the input is binary, the output with erasure option can be represented by two bits, e. A In coding theory duobinary signaling and decoding activities binary erasure channel BEC has been well studied see e. In other words 0 is never mistaken as 1 duobinary signaling and decoding activities vice versa.

They showed that decoding with the generalized erasure, which they termed ambiguity zone decoding can achieve a near-optimum performance, while retaining decoding complexity at a minimal level. As discussed above, a large class of digital communication or recording systems can be viewed as concatenated systems in which each building block may be an error control encoder, a modulator with constraints, or a channel with constraints. The conventional method of receiving such signals is to perform the inverse operations of the transmitter's building blocks, in the reverse order.

In other words, building blocks at the receiver are an inner decoder, a de-interleaver and an outer decoder. The inner decoder duobinary signaling and decoding activities to do its best in correcting errors and delivers the resultant output to the outer decoder.

Such a decoding procedure may be called a "one-path" decoding method. Such a one-path method is still susceptible to being unable to correct many error states, duobinary signaling and decoding activities a general ability to correct for many error conditions.

Accordingly, it is an object of the invention to improve error correction performance of a receiver system which receives digital data over a noisy communication channel e. It is another object of the invention to improve error correction performance of a system which retrieves data from a memory e.

The method includes the steps duobinary signaling and decoding activities In a preferred embodiment, the data making up the received data stream has been subjected to a permutation action to time-wise separate original contiguous data values.

The method subjects the quantized data stream to an inverse permutation action in producing the error-corrected data stream and further re-permutes the error-corrected data stream in step c to return it to a format identical to that of the quantized data stream before the substitution is performed.

A system incorporating the invention is schematically shown in FIG. The transmitter side is almost the same as any of the concatenated systems discussed above, except that a "permutation" module has been inserted, for generalization purposes, instead of the interleaver between the outer and inner encoders.

A carefully designed permutation module can improve the system more than a conventional interleaver, however it is to be understood that an interleaver is within the ambit of a permutation module and is a special and simple type of permutation module.

Similarly, a concatenated system without an interleaver FIG. Thus, the invention can be applied to a large class of systems with little or no modification at the transmitter side. The invention places an AZD ambiguity zone detector 10 at the receiver front end An AZD is a threshold detector or quantizer which assigns "erasure symbols" to those digits that fall in ambiguous zones duobinary signaling and decoding activities the example described below.

The output sequence from AZD 10 is then processed by passing it to concatenated decoders 14 an 16 which are connected in a loop.

Between decoders 14 and 16 is an inverse permutation module 18 in the forward path and a permutation module 20 in the feedback path. Permutation module 20 is identical to the permutation module used at the transmitter.

Thus, in a first iteration after receiving a data stream, the output sequence from AZD 14 is processed by inner decoder 14, inverse permutation module 18 which reverses the permutation inserted at the transmitter and outer decoder The decoded and error-corrected data stream is then processed by permutation module 20 which re-permutes the data stream to the form it had upon arrival at receiver input The second iteration applies the modified AZD output to the above-mentioned receiver blocks, in the same order as in the first iteration.

The cyclical decoding procedure repeats. At this point there are two options if the decoded sequence contains some unresolved erasures or detectable errors: This cyclic decoding procedure is hereafter duobinary signaling and decoding activities to as iterative decoding. However, even if the channel errors are random, i. It is easiest to explain the invention by way of an example. A concatenated system of the type shown in FIG.

As the outer code, a 7, 4 Hamming code is used and the inner code is duobinary signaling with a precoder. An n, k Hamming code is a single error correcting code, which can correct any single error that may duobinary signaling and decoding activities in a block of bits, consisting of message bits, and parity-check bits see e. Duobinary signaling is often achieved by sending a binary pulse sequence at a faster rate than is possible in ordinary transmission see e.

When the channel input is binary 0 or 1then the channel output, sampled at an duobinary signaling and decoding activities rate, should be equivalent to the sum of the present and preceding digits. Thus, the output sequence is a three-level sequence, i.

This three-level sequence cannot take on these values independently, because of the nature of its construction. For example, the output sequence should not have direct transitions from 0 to 2 or vice versa. The resultant ternary sequence, called duobinary, is a sequence with some correlation property due to the channel bandwidth constraint.

The precoder introduces a simple transformation prior to the transmission by duobinary signaling. Its purpose is to prevent a possible error propagation in the duobinary signaling and decoding activities output. The precoder maps the input binary sequence into another binary sequence, based on the following rule: Precoding of a binary sequence is similar to differential encoding usually used in DPSK differential phase shift keying.

Precoding for multi-level sequences is described in D. Duobinary signaling illustrated in this example is a simplest case of partial-response channel coding referred to in the Background of the Art.

Consider a simple packet transmission system in which there are 28 information bits in a packet, an example of which is given by the stream:. Its parity-check and generator matrices are given in systematic form by:. Then the Hamming encoder output is the following 49 bits commas are placed between code words for clarity:. Then the permutation output is obtained by reading out the above array, column by column as follows:.

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This application claims the benefit under 35 U. The present invention relates generally to an apparatus and method for generating Forward Error Correction FEC codes in a wireless data communication system. More particularly, the present invention relates to an apparatus and method for generating FEC codes having a variable rate. Also, a description will be made of an IEEE First, an IEEE Parameters used in the physical channels for the users User 1 , User 2 ,.

For example, the respective physical channels can be different from one another in input packet size, code rate, modulation order and transmission duration. A description will now be made of a physical channel for a first user User 1 , by way of example. The CRC-added user data is input to a tail bit adder a , and the tail bit adder a adds tail bits to the CRC-added user data.

The CRC is an error correction code used for correcting an error occurring due to noises in a channel transmission process, and is generally used for Forward Error Correction FEC.

Generally, convolutional codes or turbo codes are used for the FEC used in a wireless communication system. As this is well disclosed in the related references, a detailed description thereof will be omitted herein. The symbols that underwent repetition and puncturing are input to a channel interleaver a for converting a burst error occurring in the channel into a random error, and the channel interleaver a channel-interleaves the input symbols.

The channel-interleaved symbols are input to a modulator a , and the modulator a modulates the channel-interleaved symbols. In this way, data for each user is converted into one carrier signal and delivered to a radio frequency RF unit not shown.

It is not necessary that the subcarriers constituting one subchannel should always be arranged in a regular sequence in a frequency domain, and it is typical that multiple subcarriers constitute one subchannel according to a particular pattern. For example, when a given frequency bandwidth is divided into orthogonal frequencies, if there are 1 st to th subcarriers, one subchannel can be configured with 4 subcarriers of 1 st , 8 th , 16 th , 32 nd and 64 th subcarriers.

The configuration of a subchannel and the number of subcarriers constituting the subchannel are subject to change according to standards. Therefore, elements , , , , and in FIG.

When the structures of both FIGS. As illustrated in FIGS. In addition, FEC codes are used in order to overcome data errors caused by noises occurring in a radio communication channel. However, in the current physical channel for a packet transmission service, FEC codes with a fixed rate are generally used and in particular, the best codes for a given rate are used. This is because the physical channel for a packet transmission service has a characteristic of a stationary channel, such as an Additive White Gaussian Noise AWGN channel.

Therefore, there is less necessity to take the FEC codes using an adaptive rate into consideration. For example, IEEE A detailed description of the standard is well disclosed in the IEEE While the mobile communication system uses binary turbo codes, the IEEE The duo-binary turbo codes will now be described in greater detail.

As illustrated in FIG. The 2 information symbols A and B received in parallel are input in common to a first constituent encoder and a turbo interleaver The turbo interleaver interleaves the 2 parallel input information symbols A and B, and outputs the interleaved information symbols to a second constituent encoder The 2 parallel input information symbols A and B are output intact as systematic symbols, and the first constituent encoder and the second constituent encoder generate parity symbols C 1 and C 2 , respectively, using the 2 input information symbols A and B.

As a result, the 2 input information symbols are output intact as systematic symbols, and each constituent encoder generates one parity symbol. The 2 parallel input information symbols A and B are input in common to a first constituent encoder and a turbo interleaver The 2 parallel input information symbols A and B are output intact as systematic symbols, and the first constituent encoder and the second constituent encoder generate parity symbol pairs C 11 ; C 12 and C 21 ; C 22 , respectively, using the 2 input information symbols A and B.

As a result, the 2 input information symbols are output intact as systematic symbols, and each constituent encoder generates two parity symbols. A description will now be made of an encoding method performed in the duo-binary turbo encoders of FIGS.

The second constituent encoder or encodes the input information symbol pairs, and outputs a parity symbol C 2 or a parity symbol pair C 21 ; C 22 as the encoding result.

It is generally known to those skilled in the art that the duo-binary turbo codes are slightly superior to the binary turbo codes in performance gain at a high code rate.

Disadvantageously, however, the duo-binary turbo codes are inferior to the binary turbo codes in performance at a lower code rate. In addition, the duo-binary turbo codes are higher than the binary turbo codes in terms of decoding complexity, because 4 branches are used for each state in a trellis diagram.

For a system to guarantee mobility, not only should data error caused by noises occurring in a wireless communication channel be taken into consideration, but also various schemes for overcoming a data error caused by fading should be taken into consideration. For example, in order for a transmitter to actively cope with a dynamic change in signal-to-noise ratio SNR occurring in a fading channel environment, a packet modulation scheme of transmitting the same transmission packet at all times and an AMC scheme of varying a code rate of FEC codes are extensively considered.

The QCTC designates a set of turbo codes with various code rates selected by a symbol selector after code symbols, encoded from a given mother code according to a specific rule, are rearranged as shown in FIG. With reference to FIG. The generated code symbols are demultiplexed into 5 sub-blocks by a code symbol separator The separated code symbols are denoted by reference numeral Here, the respective sub-blocks undergo independent interleaving.

Among the PBRO-interleaved symbols, systematic symbols are output intact, and the PBRO-interleaved parity symbols are interlacedly rearranged by interlacers a and b. The rearrangement is achieved in such a manner that two symbols are interlaced once. Next, the sub-block comprised of interleaved systematic symbols and the 2 interlaced parity groups are arranged in a regular order and then concatenated, thus generating one new sequence.

Through a series of the processes described above, symbol rearrangement for generating QCTC codes is completed. A conventional binary QCTC design criteria is to take performance improvements of a received signal in a fading channel into consideration.

The QCTC design criteria are characterized by optimizing not only code performance, but also channel interleaving performance. The channel interleaving is generally achieved by sub-block interleaving and interlacing. According to the current HPi standard, there are some possible different combinations of modulation schemes and FEC code rates. However, there is no proposed scheme for generating and determining FEC codes supporting the possible combinations, that is, turbo codes having various code rates.

For the binary turbo codes used in a mobile communication system, that is, binary turbo codes defined in the CDMA 1x EV-DV standard, QCTC has been proposed as a scheme for providing various codes in the foregoing environments. However, QCTC is basically optimized for binary turbo codes.

Therefore, separate optimization is required when non-binary turbo codes such as duo-binary turbo codes are used as mother codes.

In particular, the use of the duo-binary turbo codes requires symbol classification and interleaving in which a characteristic of systematic symbols are taken into consideration. Accordingly, a need exists for an apparatus and method for generating desired codes and for decoding the desired codes in a high-rate wireless data system.

It is another object of the present invention to provide an apparatus and method for generating duo-binary turbo codes having various code rates, and an apparatus and method for decoding the duo-binary turbo codes in an OFDMA high-rate wireless packet data communication system in which HARQ is used.

It is another object of the present invention to provide an apparatus and method for generating duo-binary turbo codes, and an apparatus and method for decoding the duo-binary turbo codes in an OFDMA high-rate wireless packet data communication system in which various packet sizes are used, and wherein one of multiple modulation schemes and one of multiple FEC coding schemes are selected according to a channel state, a buffer state, the number of available subchannels or subcarriers , the number of OFDM symbols, and a transmission duration.

In accordance with a first aspect of the present invention, there is provided an apparatus for generating subpackets. The apparatus comprises a encoder for encoding information symbols, wherein the information symbols are fed alternatively to two input ports of the encoder; a symbol separator for demultiplexing all of the encoded symbols into two systematic symbol subblocks and two pairs of parity symbol subblocks; a channel interleaver for separately interleaving the subblocks; a symbol group generator for generating the first symbol-by-symbol multiplexed sequence of one pair of the interleaved parity symbol subblocks, the second symbol-by-symbol multiplexed sequence of another pair of the interleaved parity symbol subblocks and two systematic sequences of two interleaved systematic symbol subblocks; and a symbol selector for selecting a predetermined number of symbols from the two systematic sequences, the first symbol-by-symbol multiplexed sequence and the second symbol-by-symbol multiplexed sequence.

In accordance with a second aspect of the present invention, there is provided a method for generating subpackets. The method comprises the steps of: In accordance with a fifth aspect of the present invention, there is provided an apparatus for generating code symbols by encoding an information symbol stream according to a given code rate using a Quasi-Complementary Duo-Binary Turbo Code QC-DBTC encoder and selecting all or some of the code symbols to be transmitted from among the generated code symbols.

The apparatus comprises a QC-DBTC encoder for receiving an information symbol stream and generating QC-DBTC symbols according to a predetermined code rate; a separator for separating output symbols of the QC-DBTC encoder into a plurality of systematic symbol streams and a plurality of parity symbol streams, the systematic symbol streams being connected into one symbol stream; a plurality of interleavers for independently interleaving the parity symbol streams; a systematic symbol stream interleaver for interleaving the connected systematic symbol stream; an interlacer for interlacing the parity symbol streams in pairs; a concatenator for serial-concatenating an output of the systematic symbol stream interleaver to an output of the interlacer; and a symbol selector for selecting symbols to be transmitted according to a given data rate from the concatenated symbols.

In accordance with a sixth aspect of the present invention, there is provided a method for generating code symbols by encoding an information symbol stream according to a given code rate using a Quasi-Complementary Duo-Binary Turbo Code QC-DBTC encoder and selecting all or some of the code symbols to be transmitted from among the generated code symbols.

The method comprises the steps of receiving an information symbol stream and generating QC-DBTC symbols according to a predetermined code rate; separating output symbols of the QC-DBTC encoder into a plurality of systematic symbol streams and a plurality of parity symbol streams, the systematic symbol streams being connected into one symbol stream; independently interleaving the parity symbol streams; interleaving the connected systematic symbol stream; interlacing the parity symbol streams in pairs; serial-concatenating the interleaved systematic symbol stream to the interlaced parity symbol streams; and selecting symbols to be transmitted according to a given data rate from the concatenated symbols.

In accordance with a seventh aspect of the present invention, there is provided an apparatus for generating code symbols by encoding an information symbol stream according to a given code rate using a Quasi-Complementary Duo-Binary Turbo Code QC-DBTC encoder and selecting all or some of the code symbols to be transmitted from among the generated code symbols. In accordance with an eighth aspect of the present invention, there is provided a method for generating code symbols by encoding an information symbol stream according to a given code rate using a Quasi-Complementary Duo-Binary Turbo Code QC-DBTC encoder and selecting all or some of the code symbols to be transmitted from among the generated code symbols.

The method comprises the steps of receiving, by the QC-DBTC encoder, the an information symbol stream, and generating a plurality of systematic symbol streams and a plurality of parity symbol streams according to a given code rate, wherein the parity symbol streams are generated from the constituent encoders associated thereto and the parity symbol streams from one of the constituent encoders correspond to the parity symbol streams from another one of the constituent encoders; separating an output of the QC-DBTC encoder into systematic symbol streams and parity symbol streams; independently interleaving the systematic symbol streams and the parity symbol streams; interlacing the parity symbol pairs in pairs; concatenating the interleaved systematic symbol streams to the interlaced parity symbol streams; and selecting symbols to be transmitted according to a given data rate, from the concatenated symbols.

In accordance with a ninth aspect of the present invention, there is provided an apparatus for decoding all or some of the received code symbols generated by encoding an information symbol stream according to a given code rate using a Quasi-Complementary Duo-Binary Turbo Code QC-DBTC encoder.

The apparatus comprises a selector for inserting a predetermined code symbol in a position corresponding to a punctured symbol among received symbols; a deinterlacer for deinterlacing parity symbols among the symbols generated by the selector; a quad-symbol mapper for quad-mapping systematic symbols among the symbols generated by the selector; a plurality of deinterleavers for independently deinterleaving the quad-mapped systematic symbol streams and the deinterlaced parity symbol streams; a quad-symbol demapper for quad-demapping the deinterleaved systematic symbol stream; a code symbol concatenator for concatenating an output of the quad-symbol demapper to the deinterleaved parity symbol streams; and a QC-DBTC decoder for QC-DBTC decoding the concatenated symbol streams.

The above and other objects, features and advantages of the present invention will become more apparent from the following detailed description when taken in conjunction with the accompanying drawings in which:. Throughout the drawings, like reference numerals will be understood to refer to like parts, components and structures.

Several exemplary embodiments of the present invention will now be described in detail with reference to the annexed drawings.

In the following description, a detailed description of known functions and configurations incorporated herein has been omitted for conciseness. Therefore, an internal structure of the turbo encoder will be described with reference to FIG. This is required because in the case of duo-binary turbo codes, as illustrated in FIGS. The encoding process will now be described in detail. The change in code rate simply increases the number of parity symbol groups so that the code rate is reduced.

The turbo coding process is substantially identical to the conventional duo-binary turbo coding process. Reference numeral shows a process of separating output symbols of the duo-binary turbo encoder into systematic symbols and parity symbols, and then concatenating the separated symbols. A mapping relation of the input systematic symbols will now be described.

Quad-Symbol Mapping of Systematic Symbols. A quad-symbol mapping table is illustrated below in Table 1. The code symbol separator is substantially identical in operation to the conventional QCTC symbol separator An operation performed by the code symbol separator can be expressed as in Equation 3 to Equation 6 shown below. Sub-block Interleaving and Interlacing. The sub-block interleaving is achieved by the PBRO interleavers a , b , c , d , and e.

The interlacing is achieved by interlacers a and b. As described above, there are various possible mapping rules, and the present invention has no limitation on the mapping rules. The quad-demapping in accordance with Equation 7 or other methods is achieved by a quad-symbol demapper Next, a sub-block comprised of interleaved systematic symbols and 2 interlaced parity groups are rearranged in a regular order and then concatenated, thus generating one new sequence.